Our vision is to create a path that allows researchers to prototype their ideas without worrying about all of the intricacies of I/O, packaging, PC board design and FPGA coding.
Our goal is to shave 10-15 people-years off of a typical ASIC prototype
development process, and at the same time enable artifacts that are
of superior performance to what most research groups would have the resources to do.
We have implemented a complete system that extends from the pad ring of the chip all the way out. You just need to design your verilog to connect to our simple interface, and then make use of the pre-built components that we have developed and tested. Push it through IC Compiler, PrimeTime and Calibre to a tapeout. The rest of the way has already been thought out.
Current Users: Princeton UIUC MIT UCSD U of Cambridge Cornell Michigan
Prof. Michael Taylor
Bespoke Silicon Group
To use your silicon, you need a package.
High-performance packages are in short supply in academia;
typically people are relegated to using low-performance
PGA, QFP or QFN packages.
We created a wirebond Ball Grid Array (BGA) package that can be broadly used. It has special features that allow it to be adopted across many different chip designs.
It is suitable for chips between 3x3 mm and 6x6 mm but is most optimized for 4x4 mm and 5x5mm. You can provide our package geometry file and your bondpad coordinates to your wirebonding house, and they will tell you if it is bondable.
Traces are length-matched and impedance controlled, there is a section for PLL, and separate voltage rails for I/O and Core VDD. Although mostly re-purposable, signal wires have special capabilities (e.g. clock, pll, jtag, flow control credits) that you can take advantage of if you do assignment correctly. High-speed 100-ohm differential pairs are provided for clocks or other purposes. We can provide advice for you on how to assign your signals, just email.
|Connections to Substrate Bond Pads that go to individual balls||144||144|
|Connections to BGA internal VDD, I/O VDD, VSS and I/O VSS Planes/Rings||188||39, 41, 40, 88|
If you wish to use the package without our board, you are free to repurpose
the pins however you like, subject to the topology of the package.
However, if you have not designed a package before, we suggest you keep the BaseJump Socket Interface (pad ring arrangement) we have on the diagram, and maintain the direction and type of the pin (i.e. input, output, core Vdd, core Vss, I/O Vdd, I/O Vss), and also try to assign similar purposes to each pin.
This arrangement is optimized for signal integrity. Often times VLSI chips have a metal stack that is lower resistance in one direction than another. You should align the low resistance direction so that it connects to the sides of the package, as they have more connections to core Vdd/Vss. We place outputs on the top/bottom of the package, and allocate more I/O Vdd/Vss to these sides. Separating inputs and outputs reduces noise on inputs.
The markers indicate which part of the pad out you would keep for each size of die (e.g. 3x3,4x4,5x5). For smaller die, some bond wires will not be attached. The ball out is fixed and cannot be changed.
Before taping out your chip, you can emulate both your FPGA-firmware
and your ASIC verilog code, using the Double Trouble daughterboard.
The Double Trouble Daughterboard has two Spartan-6 FPGAs, referred to as the "Gateway FPGA" and the "ASIC FPGA". The ASIC FPGA is replaced by your real ASIC chip in the "Real Trouble" Daughterboard.
The Gateway FPGA has the code for controlling the on-board power supplies, and for forwarding data between the full-duplex high-speed source-synchronous link to the ASIC FPGA and the LPC FMC connector (which goes to an ML-605 or similar Xilinx XUP host.) It also provides resources for clock generation.
Spartan-6 was used to keep the cost low ($200 for the GW FPGA), and because it allows a large voltage range (up to 3.3V) for I/O's, and because it allows tuning of both input and output delays, allowing for high-speed I/O. Termination is external for debug probing and to allow heat to dissipated outside of the chips, which are wirebond BGA and only have 3W budgets.
The board has (unless noted, these are connected to the GW FPGA):
This daughterboard design is largely identical to the Double Trouble board
but instead will have the BaseJump BGA footprint instead of the "ASIC FPGA".
The board has been tested and is up and running in our lab.
The BaseJump High Speed FPGA Bridge is designed to work with the BaseJump BGA package.
It is synthesizeable SystemVerilog that implements a high-speed DDR source synchronous communication channel.
It is designed to be instantiated into an ASIC, and allows high speed communication through the BaseJump BGA package to another FPGA. We also support, for Double and Real Trouble, an additional hop that goes from a "gateway" FPGA over FMC to an ML-605 or Zedboard which hosts the DRAM memory system and/or and PCI-E host to a PC. The idea is that if you reuse the BaseJump Socket Interface, you can attached your RTL verilog to a working I/O system with very little effort.
Note: we refactored these files to address SystemVerilog issues across FPGA synthesis tools -- these are the updated files.
See refactored files.
This module allows an Virtex-6 ML-605 board to communicate with Linux 2.6 via the PCI Express connector. The abstraction is a number of flow-controlled FIFOs that are mapped into user space Linux. Your user code reads and writes to the FIFOs via memory-mapped I/O.Source code is available here: bitbucket.org/taylor-bsg/bsg_pci
UCSD has a PC<-->FPGA board infrastructure called RIFFA. It has a wider variety of supported boards, but focuses on DMA from DRAM. We would guess that the latency is higher but that the throughput is better.