Welcome to the BaseJump STL landing page.

See BaseJump STL (aka bsg_ip_cores) bitbucket git repo.

  1. BaseJump STL: SystemVerilog needs a Standard Template Library for Hardware Design.
    Michael B. Taylor.
    Design Automation Conference (DAC), June 2018. (pdf)

See System Verilog Coding Guidelines for BSG.

See BaseJump STL Contributor's guide.

Back to BaseJump mainpage.